`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module: AUDIO_CLK_DIV                                                        //
// Author: Rui Li, modified by Zhiyuan Lin                                      //
// Date: 3/30/2014                                                              //
// Description: This module is to devide the 100MHz by 2.                       //
//////////////////////////////////////////////////////////////////////////////////
module AUDIO_CLK_DIV(CLK_OUT, CLK, Btn_pause);
    input CLK, Btn_pause;
	 output reg CLK_OUT;
	 reg [1:0] counter = 0;
always @ (posedge CLK) begin
  if(Btn_pause == 0) begin
  counter <= counter + 1'b1;
  CLK_OUT <= counter[1];
  end
  else begin
  CLK_OUT <= 1'b0;
  end
end
endmodule